Advances in a PC's processing capability and speed has developed to the point that PC's are now utilized where previously only mainframes would suffice. Accordingly, many current PC users require the services of a wide variety of peripheral devices (e.g., printer, modem, mouse, FAX, scanner, etc.). All of the peripherals typically need to be connected to the PC via some standard connector such as the RS422 (commercial applications) or the MIL-STD-188-114 (military applications). Furthermore, current PCs operate from microprocessor speed ranges of a PC/AT (or ISA bus as it is now known)to a that of a 486 microprocessor. Currently, communication cards (as they are known in the art) are available to provide the necessary link between a PC and its peripheral devices. Unfortunately, these cards are typically limited by a particular processing speed, one or two channels of communication, and hardware set jumpers or switches defining interrupts and choice of memory access lines.
Thus, there is a need for a versatile communications card that is compatible with a variety of PC processing speeds, that offers a plurality of communications channels for the connection of a plurality of peripheral devices via standard connectors, and whose control is not governed by manually set hardware jumpers and switches.
Accordingly, it is an object of the present invention to provide a communication circuit that interfaces a processor with a plurality of application devices.
Another object of the present invention is to provide a communication circuit that interfaces a state-of-the-art microprocessor with a plurality of application devices operating at a plurality of processing speeds otherwise known as baud rates.
A further object of the present invention is to provide a communication interface circuit for simultaneously servicing a plurality of Military Standard MIL-STD-188-114 communication channels operating with a plurality of application devices.
Still another object of the present invention is to provide a communication interface circuit with software selectable interrupts and software selectable direct memory access lines.